In the design and development of semiconductor integrated circuit chips, it is often necessary to generate several iterations until an ideal design is reached. At each iteration, performance characteristics are measured and analyzed, and adjustments made to tune performance as needed. In addition, design requirements may change, requiring further changes. These issues are particularly significant for Application-Specific Integrated Circuit (ASIC) chips, which must be designed from standard elements for each new product or application.
To avoid the substantial cost and time delay to regenerate the multiple masks needed for the multiple layers of a chip upon each iteration, ASIC chip are typically provided with extra cells, or blocks of gates or other standard functional circuit elements. These cells may include complex blocks or may be simple electronic elements. When design revision is needed for a new iteration, experimental changes may be made to the existing chip by operationally connecting or disconnecting a spare cell as needed to the existing main circuitry. This enables design revision options to be tested promptly and without the substantial cost of a new mask work set. The changes may be made by focused ion beam (FIB) technology, which may be used to sever existing metal traces, or to deposit a conductive "jumper" to connect existing traces. This may be used to supply power to a spare cell, and/or to connect the input or output of such a cell to the primary circuitry, thus inserting it in the circuit.
In addition, the use of spare cells of circuit elements is also useful for implementing experimental changes proven by FIB modification in a prototype, because the needed circuit element already exists on the multiple mask layers, and it is generally necessary to change only one metal mask layer to connect the cell into the primary circuitry. Thus, the modified circuit may be manufactured without changing most existing masks, and without using the FIB techniques that are impractical for efficient and reliable manufacturing.
While the use of spare cells of circuit elements and FIB modification is effective for development of some existing integrated circuits, it is often unsuitable for the increasingly fine and dense metal patterns on many newer chips, particularly those with increasing numbers of metal layers. This is because a metal trace that one might desire to access is inaccessible beneath other metal layers. Whether one needs to sever the trace or to connect a jumper trace, it may be impractical to do so without damaging overlaying circuitry that must remain undisturbed.
The present invention overcomes the limitations of the prior art by providing an integrated circuit chip having a substrate with several overlaying metal layers. A lower metal layer is adjacent the substrate and an upper layer is spaced above the lower layer. The chip has circuitry including a number of circuit elements, and a number of access elements, each associated with and electrically connected to one of the circuit elements. Each access element includes first and second terminals in the lower layer, and an elongated span element in the upper layer. The span element has a first end overlaying and electrically connected to the first terminal and a second end overlaying and electrically connected to the second terminal. One of the terminals may be connected to provide power or a connection to the input or output of the associated circuit element. The chip may then be modified by severing the span element, or by connecting the span element to other circuitry on the chip to disable or enable operation of the circuit element.